The present invention generally relates to memory access in a computer system. More specifically, the invention relates to memory access during a DMA (Direct Memory Access) transfer.
In many processor-based systems, it is advantageous to use specialized logic rather than the processor to move large amounts of data to and from memory, thus leaving the processor free to do other work. Such specialized logic units are known as DMA (Direct Memory Access) engines. A typical DMA engine is configured by the processor with a starting memory address, a transfer size, and direction (transfer to memory or transfer from memory), then given a xe2x80x9cstart transferxe2x80x9d signal. The engine then transfers an entire block of data to or from memory without further processor intervention. The engine may notify the processor with a xe2x80x9cblock completexe2x80x9d signal when the transfer is finished.
The engine typically uses a counter, initialized to the programmed transfer size, and a current address pointer, initialized to the starting memory address. The engine transfers one byte/word/dword to or from memory by generating the proper sequence of address, data and control signals (i.e. read or write) as required by memory. The address signals are generated from a current address register. The data signals may be generated by the engine, or may be generated externally and simply passed through by the engine.
After a byte/word/dword transfer, the engine advances the current address pointer and decrements the counter. If the counter is zero, the block transfer is finished and the block complete signal is given. If the counter is non-zero, the engine transfers the next byte/word/dword.
In some applications, especially data communications, the xe2x80x9cblock completexe2x80x9d signal provided by the DMA engine at the end of each block transfer is used by other logic units as a block-rate xe2x80x9cclockxe2x80x9d signal. Using DMA block complete as a block-rate clock is simpler than generating the clock from another source, such as the sampling clock. For this reason,it would be advantageous to keep the DMA engine transferring data at all times in order to make use of the block-rate clock.
However, in some data communications applications such as TDM (Time Division Multiplex), the data stream is not continuous, so that using the DMA engine to transfer data continuously would unnecessarily occupy memory and dissipate undue power. Thus, there is a need for an invention which allows continuous use of the DMA engine without unnecessarily occupying memory.
Certain objects, advantages, and novel features of the invention will be set forth in part in the description that follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned with the practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
To achieve various objects and advantages, the present invention is directed to an apparatus and system for blocking memory access during a DMA transfer. In accordance with one embodiment of the present invention, the system includes memory, a DMA engine, and logic configured so that when a control signal is asserted, the logic blocks the DMA engine""s request for access to memory and generates an acknowledgment of the request, such that the DMA engine performs a DMA transfer without accessing data in memory.
One advantage of the present invention is that the DMA engine can be kept running continuously even when no data is available, so that the DMA engine""s block complete output signal can be used by other parts of the system as a block-rate clock. Without this invention, continuous use of the DMA engine would unnecessarily occupy memory and dissipate undue power. Another advantage of the present invention is that it requires no modification to existing DMA engine designs.